High performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), preferably covering radio frequency carriers directly, can be utilized in communications equipment. Accordingly, there lies a need for frequency and bandwidth tunable ADCs and DACs.
Referring now to FIG. 1, a four-stage sigma-delta-sigma modulator based ADC architecture, which has primarily a low-pass noise-shaping characteristic (i.e., one side of the signal pass band is at DC, and the noise is pushed to frequencies above the highest signal pass band frequency). In each stage of ADC modulator 100, there are 2 sample and hold circuits 110 and 112 used to delay the stage output by one sample clock period and combine it with the stage input, thereby producing a sampled analog integrator. The system of ADC modulator 100 uses discrete time, rather than continuous time integration, for optimum performance in higher order modulators. The modulator loop delay on noise is minimized, thereby allowing for stable operation using higher effective modulator loop gain than would be possible using continuous time integration (particularly in 1-bit output modulators). Using dual latches 114 and 116 after quantizer 118 minimizes the feedback transient responses of DACs 120 and 134 and consequently the stage output transient responses. An isolated critical first stage DAC 120 is shown to minimize undesired stage to stage interaction via feedback path 122. De-multiplexer 124 in one embodiment provides optional serial-to-parallel conversion to reduce the physical data rate where needed (i.e., reduce the data bus rate between the modulator and decimator circuits). The "Gx" and "1-Gx" gain controls G.sub.1, G.sub.2, G.sub.3, 1-G.sub.1, 1-G.sub.2, and 1-G.sub.3 are used to stabilize ADC modulator 100, while at the same time maintaining a flat response to modulator input 126 at modulator data output 128. The C1 and C2 inputs are non-overlapping, two phase sample clocks used to control the timing of the delay elements (i.e., "S/H pairs" and "latch pairs"). The first two stages 130 and 132 of ADC modulator 100 have a feedback gain control term T.sub.2 which is used to form a partial resonator at the upper frequency end of the pass band, and thereby effectively increase the pass bandwidth. In effect, part of the high frequency pass band noise is moved to the lower frequencies, which flattens and widens the pass band noise response.
Referring now to FIG. 2, a linearized model of the sigma-delta-sigma modulator shown in FIG. 1 will be discussed. FIG. 2 illustrates how the transfer function of ADC modulator 200 behaves relative to input signal X at input 210 and the quantizer noise Q.sub.N. Similar linearized models can be formed and transfer equations derived for other numbers of stages.
T feedback terms can be used around all of the paired sets of stages, thereby mostly eliminating the low-pass noise response and replacing it with a tunable band-pass response. In other words, the noise is moved out of the desired signal bandwidth that is center frequency tunable up in frequency. A decimation circuit that would be used to recover the desired resolution and reduce the sample rate would in effect utilize tunable digital frequency translation of the signal bandwidth and a fixed digital filter. When ADC modulator 200 is used as a tunable band-pass ADC, the quality factor "Q" (the ratio of the tune frequency to the signal bandwidth) is not constant, but rather decreases as the tune frequency increases. This is not a problem when the tune frequency is low relative to the modulator sample rate, which is the case when used to enhance the low-pass signal bandwidth. However, as the tune frequency approaches the Nyquist rate (F.sub.S /2), the noise shaping ability degrades substantially. Thus, there lies a need for a new architecture for a sigma-delta-sigma modulator variation that can provide tunable band-pass performance with constant Q over the sampling band. In such a modulator the noise shaping performance would preferably be basically the same regardless of the tune frequency.